supertex inc. hv9910b supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com features switch mode controller for single switch led drivers enhanced drop-in replacement to the hv9910 open loop peak current controller internal 8.0 to 450v linear regulator constant frequency or constant off-time operation linear and pwm dimming capability requires few external components for operation applications dc/dc or ac/dc led driver applications rgb backlighting led driver back lighting of ?at panel displays general purpose constant current source signage and decorative led lighting chargers ? ? ? ? ? ? ? ? ? ? ? ? ? general description the hv9910b is an open loop, current mode, control led driver ic. the hv9910b can be programmed to operate in either a constant frequency or constant off-time mode. it includes an 8.0 - 450v linear regulator which allows it to work from a wide range of input voltages without the need for an external low voltage supply. the hv9910b includes a pwm dimming input that can accept an external control signal with a duty ratio of 0 - 100% and a frequency of up to a few kilohertz. it also includes a 0 - 250mv linear dimming input which can be used for linear dimming of the led current. the hv9910b is ideally suited for buck led drivers. since the hv9910b operates in open loop current mode control, the controller achieves good output current regulation without the need for any loop compensation. pwm dimming response is limited only by the rate of rise and fall of the inductor current, enabling very fast rise and fall times. the hv9910b requires only three external components (apart from the power stage) to produce a controlled led current making it an ideal solution for low cost led drivers. typical application circuit universal high brightness led driver c dd r t r cs l1 q1 d1 c o c in hv9910b vi n gate pwmd vdd ld cs rt gn d
2 hv9910b supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com -g indicates package is rohs compliant (green) absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the speci?cations is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . parameter value v in to gnd -0.5v to +470v v dd to gnd 12v cs, ld, pwmd, gate, rt to gnd -0.3v to (v dd +0.3v) junction temperature range -40c to +150c storage temperature range -65c to +150c continuous power dissipation (t a = +25c) 8-lead soic 16-lead soic 630mw 1300mw sym description min typ max units conditions input v indc input dc supply voltage range 1 * 8.0 - 450 v dc input voltage i insd shut-down mode supply current * - 0.5 1.0 ma pin pwmd to gnd ordering information device package options 8-lead soic 16-lead soic hv9910b HV9910BLG-G hv9910bng-g 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 8 7 6 5 1 2 3 4 vin cs gnd gate rt ld vdd pwm d vin nc nc cs gnd nc nc gate nc nc rt ld vdd nc nc pwm d pin description product marking y = last digit of year sealed ww = week sealed l = lot number = green packaging yww 9910b llll y = last digit of year sealed ww = week sealed l = lot number c = country of origin* a = assembler id* = green packagin g *may be part of top marking top markin g bottom marking hv9910bng y ww llllllll ccccccccc aaa 8-lead soic (lg) 16-lead soic (ng) 8-lead soic (lg) 16-lead soic (ng) electrical characteristics (the speci?cations are at t a = 25c and v in = 12v, unless otherwise noted.) thermal resistance package ja 8-lead soic 128 o c/w 16-lead soic 82 o c/w package may or may not include the following marks: si or package may or may not include the following marks: si or notes: 1. also limited by package power dissipation limit, whichever is lower. ? v dd load current external to the hv9910b. * denotes the speci?cations which apply over the full operating ambient temperature range of -40c < t a < +125c. # guaranteed by design.
3 hv9910b supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com sym description min typ max units conditions internal regulator v dd internally regulated voltage - 7.25 7.5 7.75 v v in = 8.0v, i dd(ext) ( ?) = 0, 500pf at gate; r t = 226k ? , pwmd = v dd v dd, line line regulation of v dd - 0 - 1.0 v v in = 8.0 - 450v, i dd(ext) = 0, 500pf at gate; r t = 226k ? , pwmd = v dd internal regulator v dd, load load regulation of v dd - 0 - 100 mv i dd(ext) = 0 - 1.0ma, 500pf at gate; r t = 226k ? , pwmd = v dd uvlo v dd undervoltage lockout threshold * 6.45 6.7 6.95 v v dd rising ?uvlo v dd undervoltage lockout hysteresis - - 500 - mv v dd falling i in,max current that the regulator can supply before ic goes into uvlo # 5.0 - - ma v in = 8.0v pwm dimming v en(lo) pin pwmd input low voltage * - - 0.8 v v in = 8.0 - 450v v en(hi) pin pwmd input high voltage * 2.0 - - v v in = 8.0 - 450v r en pin pwmd pull-down resistance at pwmd - 50 100 150 k? v pwmd = 5.0v current sense comparator v cs,th current sense pull-in threshold voltage - 225 250 275 mv -40c < t a < +85c 213 250 287 t a < +125c v offset offset voltage for ld comparator * -12 - 12 mv --- t blank current sense blanking interval - 150 215 280 ns 0 < t a < +85 o c, v ld = v dd , v cs = v cs,th + 50mv after t blank - 145 215 315 -40 < t a < +125 o c, v ld = v dd , v cs = v cs,th + 50mv after t blank t delay delay to output - - 80 150 ns v ld = v dd , v cs = v cs,th + 50mv after t blank oscillator f osc oscillator frequency - 20 25 30 khz r t = 1.00m? - 80 100 120 r t = 226k? gate driver i source gate sourcing current - 165 - - ma v gate = 0v, v dd = 7.5v i sink gate sinking current - 165 - - ma v gate = v dd , v dd = 7.5v t rise gate output rise time - - 30 50 ns c gate = 500pf , v dd = 7.5v t fall gate output fall time - - 30 50 ns c gate = 500pf , v dd = 7.5v notes: 1. also limited by package power dissipation limit, whichever is lower. ? v dd load current external to the hv9910b. * denotes the speci?cations which apply over the full operating ambient temperature range of -40c < t a < +125c. # guaranteed by design. electrical characteristics (cont.) (the speci?cations are at t a = 25c and v in = 12v, unless otherwise noted.)
4 hv9910b supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com the hv9910b is optimized to drive buck led drivers using open-loop peak current mode control. this method of control enables fairly accurate led current control without the need for high side current sensing or the design of any closed loop controllers. the ic uses very few external components and enables both linear and pwm dimming of the led current. a resistor connected to the rt pin programs the frequency of operation (or the off-time). the oscillator produces pulses at regular intervals. these pulses set the sr ?ip-?op in the hv9910b which causes the gate driver to turn on. the same pulses also start the blanking timer which inhibits the reset input of the sr ?ip ?op and prevent false turn-offs due to the turn-on spike. when the fet turns on, the current through the inductor starts ramping up. this current ?ows through the external sense resistor r cs and produces a ramp voltage at the cs pin. the comparators are constantly comparing the cs pin voltage to both the voltage at the ld pin and the internal 250mv. once the blanking timer is complete, the output of these comparators is allowed to reset the ?ip ?op. when the output of either one of the two comparators goes high, the ?ip ?op is reset and the gate output goes low. the gate goes low until the sr ?ip ?op is set by the oscillator. assuming a 30% ripple in the inductor, the current sense resistor r cs can be set using: r cs = 0.25v (or v ld ) 1.15 ? i led (a) constant frequency peak current mode control has an in - herent disadvantage C at duty cycles greater than 0.5, the control scheme goes into subharmonic oscillations. to pre - vent this, an arti?cial slope is typically added to the current sense waveform. this slope compensation scheme will af - fect the accuracy of the led current in the present form. however, a constant off-time peak current control scheme does not have this problem and can easily operate at duty cycles greater then 0.5 and also gives inherent input volt - age rejection making the led current almost insensitive to input voltage variations. but, it leads to variable frequency operation and the frequency range depends greatly on the input and output voltage variation. hv9910b makes it easy to switch between the two modes of operation by changing one connection (see oscillator section). input voltage regulator the hv9910b can be powered directly from its vin pin and can work from 8.0 - 450vdc at its vin pin. when a voltage is applied at the vin pin, the hv9910b maintains a constant 7.5v at the vdd pin. this voltage is used to power the ic and any external resistor dividers needed to control the ic. the vdd pin must be bypassed by a low esr capacitor to provide a low impedance path for the high frequency current of the output gate driver. the hv9910b can also be operated by supplying a voltage at the vdd pin greater than the internally regulated voltage. this will turn off the internal linear regulator of the ic and the hv9910b will operate directly off the voltage supplied at the vdd pin. please note that this external voltage at the vdd pin should not exceed 12v. although the vin pin of the hv9910b is rated up to 450v, the actual maximum voltage that can be applied is limited by the power dissipation in the ic. for example, if an 8-pin soic (junction to ambient thermal resistance r ,j-a = 128c/ w) hv9910b draws about i in = 2.0ma from the vin pin, and has a maximum allowable temperature rise of the junction temperature limited to about t = 100c, the maximum volt - age at the vin pin would be: in these cases, to operate the hv9910b from higher input voltages, a zener diode can be added in series with the vin pin to divert some of the power loss from the hv9910b to the zener diode. in the above example, using a 100v zener diode will allow the circuit to easily work up to 450v. the input current drawn from the vin pin is a sum of the 1.0ma current drawn by the internal circuit and the current drawn by the gate driver (which in turn depends on the switching frequency and the gate charge of the external fet). i in 1.0ma + q g ? f s in the above equation, f s is the switching frequency and q g is the gate charge of the external fet (which can be ob - tained from the datasheet of the fet). application information
5 hv9910b supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com current sense the current sense input of the hv9910b goes to the non- inverting inputs of two comparators. the inverting terminal of one comparator is tied to an internal 250mv reference whereas the inverting terminal of the other comparator is connected to the ld pin. the outputs of both these com - parators are fed into an or gate and the output of the or gate is fed into the reset pin of the ?ip-?op. thus, the com - parator which has the lowest voltage at the inverting terminal determines when the gate output is turned off. the outputs of the comparators also include a 150-280ns blanking time which prevents spurious turn-offs of the exter - nal fet due to the turn-on spike normally present in peak current mode control. in rare cases, this internal blanking might not be enough to ?lter out the turn-on spike. in these cases, an external rc ?lter needs to be added between the external sense resistor (r cs ) and the cs pin. please note that the comparators are fast (with a typical 80ns response time). hence these comparators are more susceptible to be triggered by noise than the comparators of the hv9910. a proper layout minimizing external induc - tances will prevent false triggering of these comparators. oscillator the oscillator in the hv9910b is controlled by a single re - sistor connected at the rt pin. the equation governing the oscillator time period t osc is given by: t osc (s) = r t (k) + 22 25 if the resistor is connected between rt and gnd, hv9910b operates in a constant frequency mode and the above equa - tion determines the time-period. if the resistor is connected between rt and gate, the hv9910b operates in a constant off-time mode and the above equation determines the off- time. gate output the gate output of the hv9910b is used to drive an ex - ternal fet. it is recommended that the gate charge of the external fet be less than 25nc for switching frequencies 100khz and less than 15nc for switching frequencies > 100khz. linear dimming the linear dimming pin is used to control the led current. there are two cases when it may be necessary to use the linear dimming pin. ? in some cases, it may not be possible to ?nd the exact r cs value required to obtain the led current when the internal 250mv is used. in these cases, an external volt - age divider from the vdd pin can be connected to the ld pin to obtain a voltage (less than 250mv) corresponding to the desired voltage across r cs . ? linear dimming may be desired to adjust the current level to reduce the intensity of the leds. in these cases, an external 0-250mv voltage can be connected to the ld pin to adjust the led current during operation. to use the internal 250mv, the ld pin can be connected to vdd. note: although the ld pin can be pulled to gnd, the output cur - rent will not go to zero. this is due to the presence of a mini - mum on-time (which is equal to the sum of the blanking time and the delay to output time) which is about 450ns. this will cause the fet to be on for a minimum of 450ns and thus the led current when ld = gnd will not be zero. this current is also dependent on the input voltage, inductance value, for - ward voltage of the leds and circuit parasitics. to get zero led current, the pwmd pin has to be used. pwm dimming pwm dimming can be achieved by driving the pwmd pin with a low frequency square wave signal. when the pwm signal is zero, the gate driver is turned off and when the pwmd signal if high, the gate driver is enabled. since the pwmd signal does not turn off the other parts of the ic, the response of the hv9910b to the pwmd signal is almost instantaneous. the rate of rise and fall of the led current is thus determined solely by the rise and fall times of the induc - tor current. to disable pwm dimming and enable the hv9910b perma - nently, connect the pwmd pin to vdd.
6 hv9910b supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com pin description block diagram pin # function description 8-lead soic 16-lead soic 1 1 vin this pin is the input of an 8.0 - 450v linear regulator. 2 4 cs this pin is the current sense pin used to sense the fet current by means of an external sense resistor. when this pin exceeds the lower of either the internal 250mv or the voltage at the ld pin, the gate output goes low. 3 5 gnd ground return for all internal circuitry. this pin must be electrically con - nected to the ground of the power train. 4 8 gate this pin is the output gate driver for an external n-channel power mosfet. 5 9 pwmd this is the pwm dimming input of the ic. when this pin is pulled to gnd, the gate driver is turned off. when the pin is pulled high, the gate driver operates normally. 6 12 vdd this is the power supply pin for all internal circuits. it must be bypassed with a low esr capacitor to gnd (0.1f). 7 13 ld this pin is the linear dimming input and sets the current sense threshold as long as the voltage at the pin is less than 250mv (typ). 8 14 rt this pin sets the oscillator frequency. when a resistor is connected be - tween rt and gnd, the hv9910b operates in constant frequency mode. when the resistor is connected between rt and gate, the ic operates in constant off-time mode. - 2, 3, 6, 7, 10, 11, 15, 16 nc no connection po r 250m v rt pwmd ga te vd d vi n ld cs gn d s r q blanking oscillator regulator + - + -
7 hv9910b supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com 8-lead soic (narrow body) package outline (lg) 4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch 1 8 seating plane gauge plane l l1 l2 e e1 d e b a a2 a1 seating plane a a to p v iew side v iew vi ew b vi ew b 1 note 1 (index area d/2 x e1/2) vi ew a-a h h note 1 symbol a a1 a2 b d e e1 e h l l1 l2 1 dimension (mm) min 1.35* 0.10 1.25 0.31 4.80* 5.80* 3.80* 1.27 bsc 0.25 0.40 1.04 ref 0.25 bsc 0 o 5 o nom - - - - 4.90 6.00 3.90 - - - - max 1.75 0.25 1.65* 0.51 5.00* 6.20* 4.00* 0.50 1.27 8 o 15 o jedec registration ms-012, variation aa, issue e, sept. 2005. * this dimension is not speci?ed in the jedec drawing. drawings are not to scale. supertex doc. #: dspd-8solgtg, version i041309. note: this chamfer feature is optional. a pin 1 identi?er must be located in the index area indicated. the pin 1 identi?er can be: a molded mark/identi?er; an embedded metal marker; or a printed indicator. 1.
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate product liability indemnification insurance agreement. supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry an d specifications are subject to change without notice. for the latest product specifications refer to the supertex inc . (website: http//ww w. supertex.com ) ?2010 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 te l: 408-222-8888 www .supertex.com 8 hv9910b (the package drawing(s) in this data sheet may not re?ect the most current speci?cations. for the latest package outline information go to http://www.supertex.com/packaging.htm l .) doc.# dsfp-hv9910b b061209 16-lead soic (narrow body) package outline (ng) 9.90x3.90mm body, 1.75mm height (max), 1.27mm pitch symbol a a1 a2 b d e e1 e h l l1 l2 1 dimension (mm) min 1.35* 0.10 1.25 0.31 9.80* 5.80* 3.80* 1.27 bsc 0.25 0.40 1.04 ref 0.25 bsc 0 o 5 o nom - - - - 9.90 6.00 3.90 - - - - max 1.75 0.25 1.65* 0.51 10.00* 6.20* 4.00* 0.50 1.27 8 o 15 o jedec registration ms-012, variation ac, issue e, sept. 2005. * this dimension is not speci?ed in the jedec drawing. drawings are not to scale. supertex doc. #: dspd-16song, version g041309. d seating plane gauge plane l l1 l2 to p v iew side v iew vi ew a-a vi ew b vi ew b 1 e1 e a a2 a1 a a seating plane e b h h 16 1 note 1 note 1 (index area d/2 x e1/2) note: this chamfer feature is optional. if it is not present, then a pin 1 identi?er must be located in the index area indicated. the pin 1 identi?er can be: a molded mark/identi?er; an embedded metal marker; or a printed indicator. 1.
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